⚡ No corners cut — 22 Verified Multi-ECAD Benchmark Boards • 80/80 Regression Suite • 0 DRC / 0 Unconnected

Handwritten by physics. Indistinguishable from magic. Checkable to the millivolt.

Upload your unrouted Native Binary or ASCII Altium Designer (.PcbDoc), KiCad 8/9/10 (.kicad_pcb / .kicad_sch), Cadence Allegro / OrCAD (.dsn / IPC-2581 .xml), atopile (.ato), or tscircuit (.tsx) 2–4 layer design directly in the browser—with automated Embedded Footprint & Pad-Geometry Verification below. Our Calligraphy Neural Physical Synthesis Engine (v6.1.0) running in an AES-256 Encrypted Cloud Synthesis Enclave delivers a verified 0-Open, 0-DRC layout with IPC-2221 high-density 3D escape, Snowman teardrops, Picosecond Flight-Time Tuning, Zero-Install 2D/3D HTML5 Viewer, and Native Multi-ECAD + JLCPCB / PCBWay Factory .ZIP Bundle. (Need 6L–16L HDI, 0.40 mm Stacked Blind/Buried BGA escape, or Enterprise Multi-ECAD? calligraphysystems.com is currently under construction—join the early-access queue inside!)

⚡ Engine Architecture Specs (v6.1.0): Native Binary OLE2 Altium .PcbDoc Round-Trip • Picosecond Flight-Time Tuning • 3D Stacked μVias • Nodal G·V = I

⚡ Native Binary OLE2 Altium .PcbDoc & Multi-ECAD Round-Trip (v6.1.0)

True Binary OLE2 Altium Designer In & Out (.PcbDoc ↔ .PcbDoc, no ASCII export required—preserves Components6, Polygons6, Models & blind/buried via spans byte-for-byte), High-Precision Specctra (.dsn ↔ .ses), IPC-2581 <Arc>/<Via> XML, and KiCad 8/9/10.

🛠️ Picosecond Flight-Time Tuning, 3D Stacked μVias & Nodal Physics

Unconditional Picosecond Flight-Time Serpentine Tuning (ε_eff microstrip vs. stripline + via barrel delay), True 3D Layer-Span Stacked Blind/Buried Microvias (0.40 mm BGA escape), and Fail-Closed 3D Nodal Power-Drop (G·V = I) & 50Ω RF Sign-Off.

Instant Pre-Flight Quote & 350-DPI Proof Preview

❶ Step 1: Upload or Sample ($0)

Drop your board below or click a 1-Click Sample ($149 / $295 / $995). Pay $0 upfront.

❷ Step 2: Inspect 100% Proof

Verify 0 Unconnected & 0 DRC in the 350-DPI Proof Loupe (Tab 2) before paying.

❸ Step 3: Scan QR → .ZIP (5s)

Scan the Base USDC QR in the Coinbase App — your .ZIP unlocks in 5 seconds!

📤

Drag & Drop your Altium (.PcbDoc), Allegro (.dsn/.xml), KiCad (.kicad_pcb), .ato, .tsx, or .zip

3-Second Pre-Flight Intake Check · Bidirectional Multi-ECAD Round-Trip · Single-Tenant AES-256 Enclave

📱 On a Phone or No CAD File Handy? Tap to Run a 3-Second Free Live Demo: In & Out: Altium .PcbDoc • Specctra .dsn/.ses • Allegro .xml • KiCad 8/9/10 • .ato/.tsx

💻 On Your Phone? Email Yourself a Desktop Upload Link Your .kicad_pcb / .PcbDoc files are on your workstation — send yourself a 1-click desktop reminder link

📄 Intake Prerequisite (BYOF) & Free PDF Datasheet Pad-Geometry Verifier

Prerequisite: Bring Your Own Footprints (We Verify, Never Author)
Run “Update PCB from Schematic” in KiCad, Altium, or Allegro before uploading so all component footprints and netlists are embedded in your board file. We verify your existing pad geometry and synthesize placement + 100% routed copper—we do not create custom library footprints.

📄 Free Embedded Footprint & Pad-Geometry Verification (100% Free Tool)

Upload any manufacturer component datasheet (.pdf, .kicad_mod, or include PDFs inside your project .zip) to cross-check the footprints already embedded in your uploaded board file against IPC-7351B pad pitch, pad dimensions, thermal pad (EPAD), and antenna/inductor keepout rules.

🔒 Single-Tenant AES-256 Cleanroom Enclave • 6 Virtual Specialist Workers Active

🕵️ Agent-Intake: Auditing IPC-7351B Land Patterns & Keepout Corridors...

00:12 / 12:00 (11:48 rem)

Opens Remaining

36 / 48

Netlist Indexed

Teardrop Fillets

0 Fillets

IPC-2221 Snowman

DRC / VIPPO Hazards

11 Flagged

Zero-VIPPO Queue

Active Lead Worker

🕵️ Agent-Intake

U1 (LQFP-48)

🤖 Enclave Specialist Roster (Live Handoff Chain)

📡 Shrouded Enclave Activity Radar Focus: U1

                Scanning IPC-7351B Land Pattern & Courtyard on U1...
              

💬 Live Inter-Specialist Enclave Log (Component & Net-Aware)

📧 Don't want to wait at your screen? We'll ping you the second Agent-QA seals your 350-DPI Proof:

Enclave: enclave_aes256_pending (Zero Egress)

Phase 1 Initial Release: First 3 Synthesis Tiers Live ($149–$1,495)

3 Active Tiers Live • Higher Tiers in Phase 2 Queue

Tier 1 • 2L Hobbyist Breakout

$149–$195

2-Layer Only ≤ 150 pads · Single-run prototype synthesis (vs. $650+ / 7d human)

Tier 2 • 2L Dense Maker / Indie

$295–$450

2-Layer Only ≤ 250 pads · Dense 2L 3D synthesis + Zero-VIPPO DFM (vs. $1,100+ / 7d human)

Tier 3 • 4L Standard Commercial

$995–$1,495

4L Controlled Impedance + Inner Planes + 3D Nodal G·V=I Sign-Off (vs. $3,200+ / 14d human)

DFM & VIPPO Surgery

$295–$495

Zero-VIPPO paste-via surgery, thermal spokes & silkscreen

Tier 4 • 4L Dense / Altium High-Speed

$1,795–$2,495

Phase 2: Binary Altium .PcbDoc + Picosecond Flight-Time + 3D Nodal Sign-Off

Tiers 5 & 6 • 6L–16L HDI Foundry 🚧

$3,500–$14,500

6L–8L BGA/SOM ($3,500–$6,500) & 10L–16L Enterprise HDI ($7,500–$14,500)

🔒 Phase 2 Commercial & HDI Tiers (In Private Calibration): 4L Dense / Altium High-Speed ($1,795–$2,495) • 6L–8L BGA/SOM ($3,500–$6,500) • 10L–16L Enterprise HDI ($7,500–$14,500)

🚧 Phase 2 Commercial & HDI Tier (6L–16L / >250 Pads): Boards exceeding 4 Layers or 250 Pads belong to our calligraphysystems.com Industrial Foundry ($3,500–$14,500), currently held back in Phase 2 private calibration. Reserve early access below!

Board Layers

Total Pin / Pad Count

Human IPC CID+: $970 (7d)

Single-Release • 24h Queue

$149.00

✓ Under $1,000 Corporate P-Card Ready (Discretionary Engineering Expense — No PO Required)

+50% 30-Day Unlimited ECO Pass
Unlimited free pin-swap, footprint & netlist ECO re-spins for 30 days (vs. 1x single-release). ⚡ +35% Instant Enclave Rush (<45m)
Priority Cloud Synthesis Enclave lane — unlock in 15–45 mins instead of 24-hour standard queue.

📧 Engineering Email (For B2B Receipt, Pager & 30-Day ECO Re-Spins):

🛡️ Commercial EAR99 (No-ITAR), 100% Customer IP Ownership & Master Terms Attestation: I certify this is a commercial EAR99 design with NO ITAR defense articles, Customer retains 100% IP & mask-work ownership, and I accept the Master Terms of Service (v2026.11-R8) & 100% Single-Job NRE Fee Liability Cap (JSON Schedule).

Read Full Statutory EAR99 / ITAR Citations & DoD IL4/IL5 Dedicated Enclave Notice

Statutory Export & Liability Terms: I certify and agree that: (1) I am in an EAR-eligible destination (15 CFR §§ 730–774, e.g., U.S., EU/Schengen, Switzerland, Canada, Japan), this commercial EAR99 design contains NO ITAR defense articles (22 CFR §§ 120–130) or classified data, and neither I nor my entity is subject to U.S. OFAC/BIS sanctions; (2) Customer retains 100% IP & mask-work ownership (Zero AI model training; ephemeral zero-retention enclave); and (3) I accept the Customer Engineer-of-Record sign-off boundary (GEO_DRC_GROUP) and 100% Single-Job NRE Fee Liability Cap ($0.00 consequential fab/assembly liability).

🏛️ Working on ITAR (22 CFR §§ 120–130) or CUI / DoD IL4/IL5 boards? Do not upload to the public multi-tenant queue — request our Dedicated Single-Tenant Cloud Enclave (Hosted 100% by Calligraphy Systems in US-Central1 — Isolated VPC, Cryptographic Purge Certificate, Zero Code Export — <$10,000 Federal GPC Micro-Purchase Eligible — $9,500 Single-Tenant Enclave Pass) on calligraphysystems.com.

🛡️ Enclave Fair-Use Allocation: 3 Free Compiles / 24h & 10 Quotes / 24h per IP (Unlocked boards include 25/day ECO re-spins)

Public Benchmark Scoreboard vs. Quilter ($40M+ Funded)

Audited with native kicad-cli pcb drc --severity-all --schematic-parity after fresh zone fill:

Benchmark Board	Stackup	Quilter	Calligraphy v6.1.0
Project Speedrun — i.MX8M Mini + LPDDR4 SOM	8L / 1,813 pads	+313 DRC Errors	0 Opens · 0 DRC
Project Speedrun — Ethernet + M.2 Baseboard	8L / 900+ pads	+79 DRC Errors	0 Opens · 0 DRC
ColdFire 32-Bit MCU + Xilinx Spartan FPGA	4L / 825 pads	Unrouted / Congested	0 DRC · Blank-Board e2e + Snowman Teardrops
RoyalBlue 54L — Nordic nRF54L15 + 2.4 GHz RF	8L / 380 pads	Unqualified RF	0 DRC · 50Ω RF + Zero-VIPPO PASS
Multi-ECAD Round-Trip (Binary Altium `.PcbDoc` / Allegro `.dsn` / IPC-2581)	2L–16L HDI	KiCad/Import Lock-In	0.000 mm Drift · Binary OLE2 In & Out

✔ 100% Routed & Zero-DRC Guarantee — Pay Only for Verified Completion

Zero-Defect Guarantee: You are never charged unless your board reaches 100.0% routed completion with 0 DRC violations.

🔬 Live 350-DPI Copper Proof Preview

350-DPI Full-Board Locator with 3 Sharp Copper Zoom Windows

Razor-sharp 350-DPI copper inside CROP 1..3 windows Click to Zoom 🔍

🧬 Full v6.1.0 Capability Matrix • Binary OLE2 Altium, Multi-ECAD & Physics-Verified Synthesis

Complete Feature Set: From Binary Altium / Allegro / Schematic to 0-DRC Silicon

Every synthesis job automatically executes our full 8-pillar physical design, high-speed timing closure, and electrical sign-off pipeline:

1. Native Binary OLE2 Altium & Multi-ECAD

True Binary OLE2 Altium Designer In & Out (.PcbDoc ↔ .PcbDoc, preserving Components6, Polygons6, Models & blind/buried vias), Specctra (.dsn ↔ .ses), IPC-2581 XML, and KiCad 8/9/10.

2. Embedded Footprint Verification & Turnkey Placement

Upload your board with embedded footprints (Update PCB from Schematic already run)—automatically verifies IPC-7351B pad geometry and clearances, then synthesizes 2L–16L stackup, reference planes, component placement, and 3D routing.

3. PDF Datasheet Keepout Compiler

Ingests component PDF datasheets & application notes (Taoglas, Ignion, Johanson, Murata, TI, Nordic, u-blox) to enforce board-edge antenna mounting, multi-layer copper keepout windows, and galvanic isolator creepage trenches.

4. Picosecond Flight-Time (`ps`) & Skew

Unconditional picosecond flight-time closure accounting for outer microstrip vs. inner stripline effective permittivity (ε_eff), layer-span via barrel delay, and outward-facing differential-pair phase-bump selection.

5. 3D Layer-Span Stacked μVias & BGA

True 3D layer-span intersection checks allow non-overlapping blind/buried microvias (F.Cu→In1.Cu and In2.Cu→B.Cu) to stack vertically for 0.40 mm BGA / WLCSP fanout with full-radius escape clearance verification.

6. Topological Tightening & Snowman Teardrops

Topological trace-path tightening, redundant via elimination, and Snowman pad/via teardrops that shorten total wirelength by 14%+ and eliminate acute acid traps and drill breakout across all copper layers.

7. 3D Nodal G·V=I & 2.5D Return Audit

Solves the connected 3D copper conductance network (G·V = I) across outer/inner copper weights and vias for DC IR-drop sign-off, 50Ω RF return-via stitching, and 2.5D reference-plane split return-loop auditing.

8. Zero-VIPPO DFM & Multi-Seed Synthesis

Parallel multi-seed tournament synthesis inside our Cloud Synthesis Enclave plus automated 4-point DFM repair: Zero-VIPPO paste-aperture via relocation, switching-node polygon synthesis, thermal spoke repair, and silkscreen de-collision.

🔥 Live Silicon & Copper Gallery • 100% Autonomous Synthesis

See the Copper Before You Upload: Real Boards Compiled in Our Cloud Synthesis Enclave

Click any board below to inspect full-resolution 2D Zero-DRC Copper, Before/After BGA Escapes, or 3D Raytraced Renders:

Phase 1 Live Test-Drive Test-Drive All 3 Active Phase 1 Synthesis Tiers ($149 • $295 • $995)

1-Click Pre-Flight Quote or Inspect in 350-DPI Loupe

Tier 1 • 2L Hobbyist Breakout $149.00

RP2040 USB-C Breakout (2-Layer)

2-Layer ≤150 pads • QFN-56 escape + 90Ω USB-C diff-pair + Snowman teardrop fillets • 0 Opens / 0 DRC.

Tier 2 • 2L Dense Maker / Indie $295.00

StickHub 4-Port 90Ω USB Hub (2-Layer)

2-Layer ≤250 pads • 4x downstream 90Ω USB differential pairs + Zero-VIPPO DFM + Snowman fillets • 0 DRC.

Tier 3 • 4L Standard Commercial $995.00

STM32 / ESP32 Mixed-Signal Carrier (4-Layer)

4-Layer Controlled Impedance + Solid In1.Cu GND / In2.Cu Power Planes + 3D Nodal G·V=I Sign-Off + 30d ECO.

Signature Showcase ColdFire 32-Bit MCU + Xilinx Spartan FPGA Dev Kit (4-Layer · 160 Footprints · 196 Nets)

1,162 Snowman Fillets • −365.7 mm Wirelength • 0 Opens • 0 DRC

ColdFire + Xilinx FPGA 4-Layer Zero-DRC Copper

4-Layer Pro Synthesis: 196 / 196 Nets Closed 0 DRC Errors: Snowman Teardrops & 3D Nodal PASS (Click to Zoom 🔍)

ColdFire + Xilinx FPGA 3D Raytraced Render

3D Factory Raytrace (Click to Zoom 🔍)

8-Layer HDI BGA • 1,813 Pads 0 Opens · 0 DRC (vs Quilter +313 DRC)

NXP i.MX8M Mini + LPDDR4 + eMMC SOM

8-Layer i.MX8M Mini SOM Before and After

Full 32-bit LPDDR4 memory bus + PMIC power tree + fine-pitch BGA escape solved autonomously to 0 DRC errors.

8-Layer High-Speed Carrier • 900+ Pads 0 Opens · 0 DRC (vs Quilter +79 DRC)

Project Speedrun — Ethernet + M.2 + MIPI Baseboard

90Ω USB 3.0 / MIPI-DSI / CSI differential pairs, Gigabit Ethernet magnetics, Dual-SIM & M.2 Key-E routed with 0 violations.

8-Layer RF & PMIC Feather • 299 Fillets 50Ω RF + Zero-VIPPO PASS

RoyalBlue 54L — Nordic nRF54L15 + nPM1300

Ultra-compact 0.4 mm QFN escape + 299 Snowman pad fillets + 50Ω 2.4 GHz antenna keepout & return-via fencing.

✅ Verified Board Gallery & Live Physics Scorecard • 22 Multi-ECAD Benchmark Boards • 80/80 Regression Suite

Handwritten by Physics: 10 Verified Production & Complex Benchmark Boards

Every board below was synthesized autonomously through our 3D copper solver and verified against native KiCad 9 DRC (--severity-all) and connected 3D resistive nodal physics (G·V = I). Click any render to inspect in the full-screen 350-DPI optical microscope:

Cloud Benchmark Suite

80 / 80 PASS (100%)

0 Opens • 0 Copper DRC Across All 22 Boards

1. Zynq-7000 BGA-196 + DDR3

4L • BGA Escape + Ps Flight-Time • 0 DRC

2. STM32H7 + EtherCAT Controller

4L • 100Ω Diff-Pairs • 11.4 mV Drop PASS

3. TinyTapeout ASIC Carrier

4L • Dense QFN Bus Fanout • 0 DRC

4. UCF Storm Avionics & Sensor

4L • Mixed-Signal Partitioning • 0 DRC

5. ColdFire + Cyclone FPGA

4L • 32-Bit Bus + Snowman Fillets • 0 DRC

6. StickHub 90Ω USB Hub

2L/4L • 90Ω Diff-Pair + Fillets • 0 DRC

7. Interf-U High-Pin Bus Card

4L • Parallel Backplane Bus • 0 DRC

8. Antmicro SOM Baseboard

4L • High-Speed I/O Carrier • 0 DRC

9. Carte-Test Before / After

Turnkey Placement + 3D Route • 0 DRC

10. RoyalBlue 54L Isometric 3D

8L • 50Ω 2.4 GHz RF + nPM1300 • 0 DRC

Verified Benchmark Board	Source ECAD	Stackup & Scale	3D Nodal Drop (G·V=I) & RF Z₀ Receipt
NXP i.MX8M Mini + LPDDR4 SOM	KiCad 9 / IPC-2581	8L HDI • 1,813 Pads	`14.2 mV` Forward Drop PASS • 90Ω/100Ω Diff-Pair Matched
Xilinx Zynq-7000 BGA-196 + DDR3	KiCad 9 / Altium	4L HDI • 684 Pads	`12.8 mV` Core Rail PASS • Byte-Lane Flight-Time ≤ 1.8 ps
STM32H7 + EtherCAT Industrial	Altium `.PcbDoc`	4L • 520 Pads	`11.4 mV` 3V3 Nodal Drop PASS • 100Ω MII/RMII Verified
DSP-ADAU1452 4-Layer Audio DSP	KiCad 9	4L DSP • 412 Pads	`18.2 mV` VDD Drop PASS • I2S/TDM Phase-Matched + Return Vias
ColdFire MCF5249 + Cyclone FPGA	KiCad 9 / Specctra	4L • 610 Pads	`9.4 mV` Nodal Drop PASS • 1,162 Snowman Pad Fillets

🔎 Verified Physical Proof Preview • Instant Turnkey Factory Unlock

Compilation Telemetry & 350-DPI Microscopic Proof Loupe

Inspect your board’s verified DRC, Snowman teardrop fillets, and 3D nodal voltage-drop telemetry below before unlocking your native .kicad_pcb and turnkey manufacturing bundle.

Unconnected Nets

0 / 168

KiCad 9 Native DRC

0 Errors

Snowman Pad Fillets

1,162 Fillets

3D Nodal Drop (G·V = I)

14.2 mV PASS

3x Isolated 350-DPI Microscopic Proof Crops (3.24% Area Each • >90% Board Omitted 🔒)

Anti-Scraping IP Protection: Each 350-DPI proof tile is server-side cropped to 3.24% of your uploaded board’s area (<10% combined)—meaning >90% of the board is physically absent from the image files and cannot be reconstructed. The Full-Board Overview below displays crisp 1:1 component courtyards & gold pads so you can verify placement, while vortex-warping and shrouding the inter-pin copper trace layer (58×36) until unlocked:

Crop 1: Precision QFP Escape & Teardrops (3.2% Area)

0.127 mm clearance PASS • 🔍 Zoom Micro-Tile

Crop 2: BGA μVia Escape (3.2% Area)

0 unconnected · 0 shorts • 🔍 Zoom Micro-Tile

Crop 3: Zero-VIPPO & 50Ω RF (3.2% Area)

0 vias in SMD paste • 🔍 Zoom Micro-Tile

Architectural Board Locator & Redacted Copper Overview

🗺️ Full-Board Locator & Redacted Copper Map

1:1 component & pad locator (copper shrouded) • 🔍 Click Map or Crop 1/2/3

🧭 3D Isometric Board Render

Perspective-projected 3D view • 🔍 Click to Inspect

Unlock Turnkey Manufacturing Bundle

One click unlocks the native routed .kicad_pcb + factory-ready .zip archive:

Zero-Install Interactive 2D/3D HTML5 Viewer (Viewer/board_viewer_2d_3d.html) — orbit, zoom & toggle layers in any browser
Native Routed Multi-ECAD Design Files (.kicad_pcb, Native Binary OLE2 & ASCII Altium Designer .PcbDoc, Sagitta-Bounded Specctra .ses, and Cadence Allegro IPC-2581 .xml)
JLCPCB / PCBWay Factory .ZIP (Gerber X2, Excellon Drills, IPC-D-356 Netlist, BOM & Pick-and-Place CPL .csv)
High-Speed Serpentine Flight-Time (`ps`) & 3D Nodal Physics Sign-Off Certificate (G·V = I)
AES-256 Enclave Chain-of-Custody Certificate, Paid B2B Expense Invoice & 30-Day ECO Re-Spins

📁 Inspect Full Turnkey Archive Tree (calligraphy_turnkey_fab_bundle.zip — 18+ Verified Files)

├─ CAD/ routed.kicad_pcb, routed.dsn, routed.ses, routed.kicad_dru
├─ MultiECAD_Exports/ routed_altium_binary.PcbDoc, routed_altium_ascii.PcbDoc, routed_ipc2581.xml, routed_eagle.brd, routed_easyeda.json
├─ fabrication/ board_fab_gerbers.zip (RS-274X F_Cu..B_Cu, F/B_Mask, F/B_Paste, F/B_SilkS, Edge_Cuts, PTH/NPTH.drl, board.d356)
├─ Assembly/ bom_jlcpcb.csv (Grouped LCSC/MPN BOM), cpl_jlcpcb.csv (SMD Pick-and-Place Centroids)
├─ SignOff/ DELIVERY_REPORT.md, physics_qualification_report.json, enclave_chain_of_custody.json, SHA256SUMS.txt
└─ Viewer/ board_viewer_2d_3d.html (Zero-Install Offline 2D/3D WebGL Inspector)

✅ 100% Routed (0 DRC) · Instant .ZIP Unlock on Payment $149.00

⚡ Step 3: Instant Crypto Checkout — USDC / USDT (1:1 USD) $0 Gas Fee on Base • Auto-Unlocks in 5s

Send $149.00 USDC on BASE (Chain 8453)

Unique Order Deposit Address : 0x57bb5e8dad5fcc18df70c85123b76758eab0197b

📱 Open in Coinbase Wallet / Mobile Web3 App

📱 Paying with the Coinbase Phone App? Follow these 4 easy taps (60 sec):

Need USDC? If you hold USD Cash, tap Trade (bottom bar) → USDC → Buy with USD (1:1, $0 fee).
Open QR Scanner: Tap Pay (bottom-right) → tap the small [ ⛶ ] QR Scanner icon in the top-right corner and scan the QR code above.
Switch Coin to USDC on Base: If Coinbase defaults to another coin (like XRP or BTC), tap that coin name and switch it to USDC on the Base network ($0 fee).
Send & Auto-Unlock: Enter the exact $ amount above and tap Send now — this page unlocks your .ZIP automatically in ~5 seconds!

🟢 Live On-Chain Scanner Active: Checking Base blockchain every 5s — your .ZIP download will appear at the top of this box automatically!

Optional: B2B Invoice PO Fields, Card Checkout & Manual Tx-Hash Verification

🔐 Enclave Security Controls, Order Lookup & Founding Cohort Application

🟢 Phase 1 Live Now (2L & 4L PCBs) • Zero-Key Streamable HTTP MCP Server

`@calligraphysystems/mcp` — Autonomous Physical Synthesis for Claude Code, Cursor & Windsurf

Live Today without an API Key (Phase 1 — 2L & 4L Boards): Any Model Context Protocol (MCP) client can connect directly to https://calligraphyeda.com/api/v1/mcp via JSON-RPC 2.0 Streamable HTTP and call calligraphy_list_gallery_boards, calligraphy_preflight_audit, calligraphy_compile_board, calligraphy_get_job_status, and calligraphy_verify_stablecoin_payment right now (governed by fair-use per-IP limits: 10 quotes/day, 3 compiles/day).

⚡ Instant Zero-Key Connection • Streamable HTTP JSON-RPC 2.0 (`2025-11-05` / `2024-11-05`) • Up to 50 MB Uploads

Connect Claude Code, Cursor, or Windsurf in 10 Seconds

Option A — 1-Line Claude Code CLI Command:

claude mcp add --transport http calligraphy-eda https://calligraphyeda.com/api/v1/mcp

Option B — Cursor / Windsurf / Claude Desktop (mcp_config.json):

{
  "mcpServers": {
    "calligraphy-eda": {
      "url": "https://calligraphyeda.com/api/v1/mcp"
    }
  }
}

Option C — 1-Click Starter Prompt for Claude Code / Cursor:

Use the calligraphy-eda MCP server to list the conquered benchmark boards and run a pre-flight quote on the 2l_rp2040 sample board

🔑 Wave 2 Enterprise & 6L–16L HDI Queue • Dedicated API Key Zero Spam • Batch Key Drops

Reserve Your Wave 2 6L–16L HDI & High-Volume CI/CD API Key

Phase 1 (2L & 4L boards) is live right now without an API key. Reserve a dedicated CALLIGRAPHY_ENCLAVE_API_KEY for 6L–16L high-speed/RF boards and high-volume GitHub Actions hardware CI/CD pipelines (25–100 compiles/day).

Developer / Work Email *

GitHub / X Handle or Team

Primary AI Agent + Hardware Workflow

Prefer drag-and-drop in the browser instead of MCP?

Live Phase 1 Agent Terminal Session (2L & 4L)

Live Today • No API Key Required

> Calling tool `calligraphy-eda:calligraphy_compile_board` (Streamable HTTP)...
[Calligraphy Neural Physical Synthesis Engine] Ingesting `motor_ctrl_4l.kicad_pcb`...
  ✓ Enclave Ingest (AES-256 Ephemeral RAM Disk): `enclave_aes256_job_94f8a21b`
  ✓ Stage 1/5: Neural Topology & Subcircuit Graph Embedding...
  ✓ Stage 2/5: Multi-Layer Electromagnetic Field Conditioning...
  ✓ Stage 3/5: Deep Physical Trace Synthesis & Snowman Pad Filleting (142/142 nets)
  ✓ Stage 4/5: 3D Nodal Power-Integrity (G·V=I) & Zero-VIPPO Verification (0 DRC)
  ✓ Stage 5/5: Packaged Interactive 2D/3D HTML5 Viewer + JLCPCB/PCBWay Factory .ZIP

🔍 Preview 350-DPI Proof Loupe:
   https://calligraphyeda.com/?enclave_job=job_94f8a21b

💳 Unlock 3D HTML5 Viewer + Routed .kicad_pcb + Factory .ZIP ($995.00):
   Option A (Human Card / Apple Pay): https://checkout.stripe.com/c/pay/cs_live_calligraphy_94f8a21b
   Option B (Autonomous AI-Agent Wallet — USDT / USDC on Base / Arbitrum / Polygon / Ethereum):
   > Calling `calligraphy_verify_stablecoin_payment(job_id="job_94f8a21b", token="USDC", network="base", tx_hash="0x...")`
   ✓ Verified On-Chain Settlement & Private HMAC-SHA256 Receipt → Unlocked `.zip` Bundle!

🔒 Fair-Use Enclave Protection: Zero-key Phase 1 remote HTTP MCP calls are governed by per-IP rate limits (10 quotes/day, 3 compiles/day; 2L & 4L boards). Use calligraphy_request_ip_whitelist for higher team quotas.